GATE 1991 modified

Question

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is 10 ns. Also assume that the setup time for the JK inputs of the flip flops is negligible.

What if the clock was asynchronous then it will be 40ns?

Comments

I didn't get it. What do u mean by "clock was asynchronous"?

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@rishabh

if ouput of AND gate was given as clock

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Then the diagram needs to be changed. no?

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@rishabh

Yes , its an image and i cannot make modification to it .....so am asking to assume that way and then predict the output