Digital test question about shift register.

Question

Comments

4 pulse??

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My ans was too 4 clocks cycle.

But ans is given 7 pulse. I think 7 pulse is wrong answer. What about you?

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t	pulse
0	1100
1	1001
2	0011
3	0110
4	1100

 we need 4 pulses..

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SOLUTION:

Answer 1

Here serial input is: ((Q₁⊕ (Q₂⊕Q₃))

Clock cycle	Q0	Q1	Q2	Q3
Initial clock cycle	1	1	0	0
1st clock cycle	1	1	1	0
2nd clock cycle	0	1	1	1
3rd clock cycle	1	0	1	1
4th clock cycle	0	1	0	1
5th clock cycle	0	0	1	0
6th clock cycle	1	0	0	1
7th clock cycle	1	1	0	0

we need 7 clock pulses to get initial state.

Comments

@ Hira Thakur

Actually what we understood about the shift register concept i.e.

In the Right Shift register take the input of SI (First bit -> LSB bit) to the MSB flip-flop to LSB flip-flop.

In the Left Shift register take the input of SI (First bit -> MSB bit) to the LSB flip-flop to MSB flip-flop.

Because I have done Many questions in this concept, Even Gate also asked such kind of questions where Order of flip-flop matter. Please help me find the right concept for such kind of questions because here is ambiguity.