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Consider that the memory is byte addressable with size 16 bits, and the program has been loaded starting from memory location (2000)10. What will be the return address saved in the stack, if an interrupt occurs while the CPU has been halted after executing the HALT instruction?

in CO and Architecture by Loyal (9.3k points) | 472 views
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2016??
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2018 ....
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I think it should be 2018 as next instruction address will be pushed..
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Yes, 2018 is the answer. As per given solution, they have answered it as 2016 so I just wanted to confirm it.
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The answer should be 2016 As halt instruction is a kind of loop instruction whose branch address is the same halt instruction address only. 

It is given in the question that after executing the halt instruction. So when interrupt occur CPU will push next instruction address which is previous instruction address only which is 2016 because as I mentioned earlier it is a kind of loop instruction.

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any reffernce for you statement about loop.
+1

@Shubhanshu

"Interrupt comes during the halt instruction" and "Interrupt comes after halt instruction", both are same. Because interrupt are served only after execution of current instruction.

After HALT instruction CPU enters a HALT state and if an interrupt happens the return address will be that of the instruction after the HALT. 

Ref: https://gateoverflow.in/1058/gate2004-63

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So what happens when the interrupt not occur in the system, then what should be the address in PC?
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execution would be continued sequentially
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You mean to say next address (without interrupt) will be of next instruction to Halt instruction.
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I meant to say that when nothing is there for CPU to run then OS would schedule a lowest priority idle task until an interrupt occurs. Now, this may be HLT instruction or may not be. It is processor specific. For Intel processors, staying idle traditionally meant running the halt instruction.

So for GATE purpose, it is safe to assume that the address of the instruction after the HALT is pushed onto the stack.

Having said that I'm still not sure if it is correct and that's why I asked this question. I have also put this question on GateOverflow FBgroup. 

If I go according to previous year paper answer should be 2018 and we all know that GO answers are 100% correct!

1 Answer

–1 vote

Byte addressable with 16 bits.

Thus, 1 word = 2 bytes.

After 5 instructions, it must be

2000+2*2+2*2+1*2+1*2+2*2 = 2016

As an interrupt occurs executing the HALT instruction, the return address (in decimal) saved in the stack will be the address of the halt instruction.

Reference :

http://www.geeksforgeeks.org/gate-gate-cs-2004-question-63/

by Loyal (7.8k points)
+1
Here the answer is right but the explanation is not. Please refer gateoverflow solution. I have mentioned it in my above comment. you'll get to know.

The answer should be 2018
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What @Shubhanshu said is right.

An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. The halt state indicator is set by the added interrupt of the CPU is in a halt state at the time of interruption. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted. The Halt instruction is re-executed by the RESUME instruction if the halt state indicator remains set at the time of restoration. As a result, a system integrator or OEM may provide transparent system level interrupts with automated halt state restart that will operate reliably in any operating environment, and be relieved of the burden of managing halt state restart.

Reference :

http://www.google.sr/patents/US5291604

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From the x86 instruction manual ---- > If an interrupt  is used to resume execution after a HLT instruction, the saved instruction pointer  points to the instruction following the HLT instruction. [1]

here in this question they also asked  ..If an interrupt occurs while the CPU has been halted AFTER executing the HALT instruction,

then the return address (in decimal) saved in the stack will be starting address of next instruction that is 2018.

http://x86.renejeschke.de/html/file_module_x86_id_134.html

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I'm not sure but even in made easy notes, it's written that if an interrupt occurs when the CPU has been halted after executing the HALT instruction, return address of HALT instruction is saved in the stack.
+1

https://gateoverflow.in/1058/gate2004-63

Go through all the answers and comments in this question. You will get to know.

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I read that post. But if gate gives marks to that answer, what are we supposed to mark :/
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So, is it important for the program to have interrupt just after halt instruction to read the next following instruction?
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In the x86 computer architecture, HLT (halt) is an assembly language instruction which halts the central processing unit (CPU) until the next external interrupt is fired.[1] Interrupts are signals sent by hardware devices to the CPU alerting it that an event occurred to which it should react. For example, hardware timers send interrupts to the CPU at regular intervals.

The HLT instruction is executed by the operating system when there is no immediate work to be done, and the system enters its idle state.

Reference : https://en.wikipedia.org/wiki/HLT_(x86_instruction)

I think a Halt is always followed by an interrupt.

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@Anu007

I think Interrupt is the only case where CPU reads the next instruction to halt instruction, not the same HALT instruction.

Is this correct?

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