MADEEASY

Question

The 3-bit ripple counter (shown below) is to be designed as a MOD 4 counter

What is the best architecture of the ‘Logic gate’?

A. a 3-bit input AND gate

B. a 2-input AND gate

C. a NOT gate

D. a wire connection (no logic gate needed)

Ans is given D but i think ans should be C 

Please Explain

Comments

Me too got same answer....

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I guess NOT gate wont be possible, even though its the only gate with single input and gate logic block has given only single input Q2. The desired count sequence is
00
01
10
11

All above have Q2=0. NOTting will never make above above sequence happen. Initial Q2 is 0. So it will keep clearing flip flops after every clock input.

Correct me if am wrong. I have given answer below.

Answer 1

It's an active high clear terminal i.e. clear will be inactive when Cr=0 and will be active when Cr=1.

See the diagram carefully.

http://verticalhorizons.in/preset-and-clear-in-digital-electronics/

Comments

The desire count sequence will be
00
01
10
11

After 11 we should reset the logic. So the logic gate should be AND(Q1,Q0).
But the diagram shows only Q2 is input to logic gate, which I feel is wrong.
The madeeasy solution has given the counting sequence:
000
001
010
111 <- first time Q2 becomes high

and then it says since Q2 becomes high in 4th count, we can apply it straight to all clear.
But that counting sequence is simply wrong. Q2 does get HIGH in last count. Last count would be 011 as I stated in first sequence.
The answer should be option B - 2 input AND gate.

Answer 2

The desire count sequence will be
00
01
10
11

After 11 we should reset the logic. So the logic gate should be AND(Q1,Q0).
But the diagram shows only Q2 is input to logic gate, which I feel is wrong.
The madeeasy solution has given the counting sequence:
000
001
010
111 <- first time Q2 becomes HIGH

and then it says since Q2 becomes HIGH in 4th count, we can apply it straight to all clear inputs.
But that counting sequence is simply wrong. Q2 does not get HIGH in last count. Last count would be 011 as I stated in first sequence.
The answer should be option B - 2 input AND gate.

Also if the option has two input AND gate, then how the logic gate block in the diagram has only Q2 as input, i.e. single input??? Yess they can always have AND(Q2,Q2)=Q2 and AND(Q2,Q2')=0, but that sounds stupid.

Hence the diagram is wrong.  Madeeasy solutions are wrong.
Hence proved. ;p

Correct me if am wrong....

Answer 3

D is the answer , this is a simple one .

SEQUENCE we want is { 000 ,001 ,010, 100, 000}

also clr is active high.

we have clear the FF's once sequence is 100. So this can be easily done by directly connecting Q2 to clr .(once Q2 become 1 clr is active and reset the sequence)