Given then processor fetches instructions at a rate of 1 MIPS, i.e. 1 instruction per 1 micro second. For simplicity of analysis lets assume clock cycle is also 1 micro second.
Now DMA module transfers at $\frac{9600}{8} = 1200$ bytes = 1200 characters per second. Therefor 1 Byte or 1 character transfers in every 833 micro second.
So, DMA will invoke in every 833th cycle and transfers a byte.
here $x+1 = 833 \ cycles$ . Without any DMA activity cpu would have been busy all the time (all 833 cycles). But because of DMA last cycle will be utilized by DMA where cpu remains idle. Slowdown = $\frac{(833-832)}{833}*100$ % = 0.12 %
P.S. : Here we have deliberately neglected MEM request invoked itself by CPU or assuming such MEM delay as a part of CPU work. Not contributing to slowdown caused by DMA.