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What is the best architecture of the ‘Logic gate’?

  • a 3-bit input AND gate
  • a 2-input AND gate
  • a NOT gate
  • a wire connection (no logic gate needed)
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 its up counter , in 4th clock pulse, we need to make Q3 bit as 0 in order to get mod 4 counter. so, NOT gate is required as clear inputs are active low.

Clock Q3 Q2 Q1
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
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as this is asynchronous circuit Q0n= Q0' for every signal

Q1n= Q1' (for Q0 1->0 transaction as its negative edge trigger )

Q2n=Q2' (for Q1   1->0)

Q0 Q1 Q2 Q0n Q1n Q2n
0 0 0 1 0 0
0 0 1 1 0 1
0 1 0 1 1 0
0 1 1 1 1 1
1 0 0 0 1 0
1 0 1 0 1 1
1 1 0 0 0 1
1 1 1 0 0 0

so 000->100->010->110-> 001 when Q2 is 1 it will clear and maintain mod 4 properties  so here directly Q2 gives 1 after 4 state so direct connection is enough ,no logic is needed .

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