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A machine has a $32-bit$ architecture, with $1-word$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________
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what do 1-word long instructions mean?

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one word instruction means .. the size of instruction is one word i.e. 32 bit.

$64$ registers means $6$ bits $(\lceil \log_2 64 \rceil = 6)$ for a register operand. So, $2$ registers operand requires $12$ bits. Now, $45$ instructions require another $6$ bits for opcode $(\lceil \log_2 45 \rceil = 6)$. So, totally $18$ bits. So, we have $32 - 18 = 14$ bits left for the immediate operand. So, the max value will be $2^{14} - 1 = 16383$ (as the operand is unsigned we do not need a sign bit and with $14$ bits we can represent from 0 to $2^{14} -1$)
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 Mode Opcode Operand

Assuming this is the Instruction format why is mode bit not used ?
as in
1 bit for Mode
then 6 bit for Opcode
12 for Operand
and then 13 the Operand ?

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why do we need a mode bit?
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TO specify the mode as in immediate mode.
Is this Concept of mine wrong ?
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we don't need it and opcode can tell it.
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I know this is silly but still, why 2 fields for operands are required when for immediate addressing mode we require only 1for  opcode 1 field for register and 1 field for the immediate operand i.e. for example

Mov R ,#25h

Or else if we consider only register mode then format is like

Mov A,R

???? It appears to me as if u have combined both this modes .please correct me if i am wrong
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@Arjun Sir: They never mentioned that the word size was 32bit wide, how did you get the max length of one instruction ?
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@Dinesh

It needs to support 45 instructions, which have an immediate operand in addition to two register operands

@vignesh

32-bit architecture, with 1-word long instructions

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We dont need any mode bit. This simple instruction would look like below -

Opcode(6bit), Reg_Operand1(6bit), Reg_Operand2(6bit), Immediate Operand(14 bit)
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sir if we had to show sing bit then it would be (213-1 ) ,(-1 because we represent instr 0 to 31), is im thinking correct?  ,

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yes, but we also need to know how signed number is represented then (sign-magnitude, 2's complement etc)
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Thanks
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Mr. @Arjun please tell me what does this line "...It needs to support 45 instructions which have an immediate operand..." mean? Does it mean:

that the processor supports 45 different kinds of instructions and each instruction has one immediate operand,

or there are 45 instructions inside a single opcode? (never heard of it, but idk if that can happen),

or is the instruction 45 bits long,

or something else?
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@habedo007 it means there are 45 different kinds of instruction but to even refer any one of them we need 6 bits.
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Why we are taking log on the number of registers to get the size of each register?
 ⌈log45⌉=6 bit opcode R1 ⌈log64⌉=6 bit R2 ⌈log64⌉=6 bit remaining 14 bit oprand

It needs to support 45 instructions,   means types of instruction supported is of45

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how to know operand are 6 bit means register are 64 bit so what are relation between register and operand size .?
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Instruction size if of 32 bits.

according to given information here we have 2 different types oprands and one opcode.

so first find register mode oprand bits, how -> given total 64 rigesters, take log(64)=6

now find opcode field bits, how -> given 45 types of instructions, take ceil{log(45)}=6

now find  immediate operand field bits, how -> total bits- other field bits

= 32 - (6+6+6)    (2 times 6 bcz two register oprands given)

= 14

*note: base of log is 2.

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@mint why here we left other remaining bits for 45 instrustions means from 2^6=64

45 will b in use so some will left ...why we not use them ?

### Since 2^14=16384(from 0 to 16383)

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if the immediate operand is a signed integer, then the maximum value of the immediate operand is....??

-2n-1  to (2n-1 -1)....????

OR

(-2n-1 -1)  to (2n-1 -1)....???

+1

-2n-1  to (2n-1 -1)

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okk.. :) means we use 2's complement here to represent signed integer...
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yes, as per my knowledge but i m not 100% sure, can you tag someone who can verify it?
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let me make u 100% sure.. :) I just go through this fact right now and sharing with you also...

1. Unsigned: It consist only positive value i.e 0 to 255.

2. Signed: It consist both negative and positive values but in different formats like

• -1 to -128
• 0 to +127

And this all explanation is about 8 bit number system.

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Thank You :)
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signed = -(-2n-1 -1)  to (2n-1 -1).

2's complement = 2n-1  to (2n-1 -1)

1's complement = (-2n-1 -1)  to (2n-1 -1).

unsigned = (0)  to (2n -1).

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Had it been 2-word long instruction ,the instruction length would be 64-bit long ?

@MiNiPanda
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@HeadShot Yes. Then the no. of bits for operand would increase.