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A machine has a $32-bit$ architecture, with $1-word$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________
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what do 1-word long instructions mean?

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one word instruction means .. the size of instruction is one word i.e. 32 bit.

$64$ registers means $6$ bits $(\lceil \log_2 64 \rceil = 6)$ for a register operand. So, $2$ registers operand requires $12$ bits. Now, $45$ instructions require another $6$ bits for opcode $(\lceil \log_2 45 \rceil = 6)$. So, totally $18$ bits. So, we have $32 - 18 = 14$ bits left for the immediate operand. So, the max value will be $2^{14} - 1 = 16383$ (as the operand is unsigned we do not need a sign bit and with $14$ bits we can represent from 0 to $2^{14} -1$)
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 Mode Opcode Operand

Assuming this is the Instruction format why is mode bit not used ?
as in
1 bit for Mode
then 6 bit for Opcode
12 for Operand
and then 13 the Operand ?

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why do we need a mode bit?
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TO specify the mode as in immediate mode.
Is this Concept of mine wrong ?
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we don't need it and opcode can tell it.
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I know this is silly but still, why 2 fields for operands are required when for immediate addressing mode we require only 1for  opcode 1 field for register and 1 field for the immediate operand i.e. for example

Mov R ,#25h

Or else if we consider only register mode then format is like

Mov A,R

???? It appears to me as if u have combined both this modes .please correct me if i am wrong
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@Arjun Sir: They never mentioned that the word size was 32bit wide, how did you get the max length of one instruction ?
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@Dinesh

It needs to support 45 instructions, which have an immediate operand in addition to two register operands

@vignesh

32-bit architecture, with 1-word long instructions

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We dont need any mode bit. This simple instruction would look like below -

Opcode(6bit), Reg_Operand1(6bit), Reg_Operand2(6bit), Immediate Operand(14 bit)
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sir if we had to show sing bit then it would be (213-1 ) ,(-1 because we represent instr 0 to 31), is im thinking correct?  ,

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yes, but we also need to know how signed number is represented then (sign-magnitude, 2's complement etc)
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Thanks
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Mr. @Arjun please tell me what does this line "...It needs to support 45 instructions which have an immediate operand..." mean? Does it mean:

that the processor supports 45 different kinds of instructions and each instruction has one immediate operand,

or there are 45 instructions inside a single opcode? (never heard of it, but idk if that can happen),

or is the instruction 45 bits long,

or something else?
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@habedo007 it means there are 45 different kinds of instruction but to even refer any one of them we need 6 bits.
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Why we are taking log on the number of registers to get the size of each register?
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It has 64 registers, each of which is 32 bits long

what that $32$ bits long means? Is it mean instruction size $32$ bits or register size 32 bits?

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Hi! After we have allocated 12 bits for registers, we are left with 20 bits and we need to represent 45 opcodes and unsigned int with them. Why can't we we say the answer is pow(2,20) - 45? Can opcode and int. Not share the bits?

It will be very helpful if someone clarifies this.
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@subho16 I have the same confusion. In https://gateoverflow.in/551/gate1992-01-vi @Arjun sir used as many bits as possible, we can do the same here and increase the range. Why was this not done? Is it because it is not clear how the value of the immediate will be interpreted?

Another example: https://gateoverflow.in/204126/gate2018-51

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Each of the $45$ instructions must support $n$ bit immediate operand -- it must be able to use all immediate operand variants from $0$ to $2^n-1.$ Now when we use $6$ bits for $45$ opcodes, we are losing some encodings -- but even if we use them can we increase the range of the immediate operand?
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but even if we use them can we increase the range of the immediate operand?

Thanks, I got it. Even if we were to use the lost encodings, not every opcode would be able to use the range increased above 2^n -1.

Here is one such encoding that uses expanded opcode:

0-5 : first register operand

6-11: second register operand

Bits after 11:

1. For the first 32 opcodes: 6 bits needed ( the format is 0 _ _ _ _ _ ), 14 bits left for immediate value
2. For the next 8 opcodes:  5 bits needed (1 0 _ _ _ ), 15 bits for immediate value
3. For next 4 opcodes: 5 bits needed (1 1 0 _ _ ), 15 bits for immediate value
4. For the last opcode : 3 bits needed (1 1 1), 17 bits immediate value.

So for just one opcode we will get immediate value range of 0 to 2^17-1.

Clearly, not every opcode gets equal range of immediate value. The question never said that all opcodes need equal range for immediate value, but I think it is valid to assume that immediate operands should have same range across all opcodes if nothing else is specified. is this correct?

 ⌈log45⌉=6 bit opcode R1 ⌈log64⌉=6 bit R2 ⌈log64⌉=6 bit remaining 14 bit oprand

It needs to support 45 instructions,   means types of instruction supported is of45

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how to know operand are 6 bit means register are 64 bit so what are relation between register and operand size .?
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Instruction size if of 32 bits.

according to given information here we have 2 different types oprands and one opcode.

so first find register mode oprand bits, how -> given total 64 rigesters, take log(64)=6

now find opcode field bits, how -> given 45 types of instructions, take ceil{log(45)}=6

now find  immediate operand field bits, how -> total bits- other field bits

= 32 - (6+6+6)    (2 times 6 bcz two register oprands given)

= 14

*note: base of log is 2.

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@mint why here we left other remaining bits for 45 instrustions means from 2^6=64

45 will b in use so some will left ...why we not use them ?

### Since 2^14=16384(from 0 to 16383)

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if the immediate operand is a signed integer, then the maximum value of the immediate operand is....??

-2n-1  to (2n-1 -1)....????

OR

(-2n-1 -1)  to (2n-1 -1)....???

+1

-2n-1  to (2n-1 -1)

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okk.. :) means we use 2's complement here to represent signed integer...
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yes, as per my knowledge but i m not 100% sure, can you tag someone who can verify it?
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let me make u 100% sure.. :) I just go through this fact right now and sharing with you also...

1. Unsigned: It consist only positive value i.e 0 to 255.

2. Signed: It consist both negative and positive values but in different formats like

• -1 to -128
• 0 to +127

And this all explanation is about 8 bit number system.

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Thank You :)
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signed = -(-2n-1 -1)  to (2n-1 -1).

2's complement = 2n-1  to (2n-1 -1)

1's complement = (-2n-1 -1)  to (2n-1 -1).

unsigned = (0)  to (2n -1).

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Had it been 2-word long instruction ,the instruction length would be 64-bit long ?

@MiNiPanda
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@HeadShot Yes. Then the no. of bits for operand would increase.