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a direct-mapped cache of the size of 4 blocks. The main memory block access sequences are 0,1,2,3,4,1,2,3,0,4,0
No. of compulsory misses, conflict misses and capacity misses?

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0      A                                                       compulsory miss ->A

1      A                                                       conflict miss -> B

2      A                                                       capacity miss -> C

3      A

4      A

1      HIT

2      HIT

3      HIT

0      C (as from last access of 0 to this access we have 4 unique accesses and 4-1=3 unique blocks so capacity miss)

4      C (as from last access of 4 to this access we have 4 unique accesses and 4-1=3 unique blocks so capacity miss)

0      B (as from last access of 0 to this access we have 1 unique accesses and 4-1=3 unique blocks so conflict miss)

so  compulsory miss = 5 conflict miss = 1 capacity miss = 2

and total miss=7

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