1 votes 1 votes a direct-mapped cache of the size of 4 blocks. The main memory block access sequences are 0,1,2,3,4,1,2,3,0,4,0 No. of compulsory misses, conflict misses and capacity misses? CO and Architecture cache-memory misses + – Raj_Choudhary asked Dec 4, 2017 Raj_Choudhary 1.6k views answer comment Share Follow See all 22 Comments See all 22 22 Comments reply Show 19 previous comments Prateek Raghuvanshi commented Dec 13, 2018 reply Follow Share can anybody help me why 0,4 are taken as capacity miss not conflict miss?? 0 votes 0 votes Prateek Raghuvanshi commented Dec 13, 2018 reply Follow Share i think 0,4 are also conflict miss because if they are capacity miss then increasing cache size these misses should not be there but still these are misses means these are not capacity ,these are conflict misses . 0 votes 0 votes codingo1234 commented Dec 31, 2018 reply Follow Share @ Prateek Raghuvanshi ,check this ans https://gatestack.in/t/conflict-miss-compulsory-miss-capacity-miss-direct-mapped-cache/487/2 after reading it I came to conclusion that Compulsory misses are 5 Capacity misses =1(second last 0) Conflict miss=2(last 4 and last 0) please someone just confirm it 0 votes 0 votes Please log in or register to add a comment.
2 votes 2 votes 0 A compulsory miss ->A 1 A conflict miss -> B 2 A capacity miss -> C 3 A 4 A 1 HIT 2 HIT 3 HIT 0 C (as from last access of 0 to this access we have 4 unique accesses and 4-1=3 unique blocks so capacity miss) 4 C (as from last access of 4 to this access we have 4 unique accesses and 4-1=3 unique blocks so capacity miss) 0 B (as from last access of 0 to this access we have 1 unique accesses and 4-1=3 unique blocks so conflict miss) so compulsory miss = 5 conflict miss = 1 capacity miss = 2 and total miss=7 shubham gupta 4 answered Sep 28, 2019 shubham gupta 4 comment Share Follow See all 0 reply Please log in or register to add a comment.