test series

Question

Consider 6 stage pipeline (S₁ , S₂, S₃, S₄, S₅, S₆) which allows all the instructions except branch instructions. Processor stops fetching the following instruction after the branch until the target address is available. Target address is available in the S₄ stage. Program contain 40% of branch instructions. All the stages are balanced with a 2.3 GHz clock. MIPS rate of the processor is ________ (in 2 decimal places).

Answer 1

Branch penalty = 3

40% are branch instruction , avg #f stalls created due to branch instruction = 0.4*3 =1.2

avg execution time for a instruction = (1+#f stalls )* CT

= (1+1.2)*1/2.3GHz = 0.956  nsec

on avg, 1 instruction takes ---------------0.956nsec, in 1 sec = 1045.45 MIPS

Comments

2.3 GHz is given