edited by
4,636 views

3 Answers

Best answer
14 votes
14 votes
Search in associative memory is parallel. For k-way associativity we can have k comparators which compares the tag bits of 'k' blocks in parallel. We can't increase 'k' beyond a limit due to hardware limitation.
2 votes
2 votes

In any sort of associative memory — be it fully associative or x-way associative, we use something called "comparators" to search for the data we require.

The comparators compare the related tags in parallel, and it employs an OR gate because even if one tag matches, we need to know.

In fully associative memory, we have a tag for each possible location (all the cache lines) of the required data. Hence, we have tags, and need n comparators — all of which compare parallelly.

In x-way set associative memory, the data can be in any of the x lines of a known set. For which we need x comparators which again, compare parallelly.

 

Option A

0 votes
0 votes
A type of computer memory from which items may be retrieved by matching some part of their content, rather than by specifying their address (hence also called associative storage or Content-addressable memory (CAM)
Associative memory makes a parallel search with the stored patterns as data files.
Answer:

Related questions

7 votes
7 votes
4 answers
1
jenny101 asked Jun 18, 2016
9,035 views
Consider a direct mapped cache with $64$ blocks and a block size of $16$ bytes. To what block number does the byte address $1206$ map todoes not map$6$$11$$54$
4 votes
4 votes
5 answers
2
go_editor asked Jun 23, 2016
3,534 views
In DMA transfer scheme, the transfer scheme other than burst mode iscycle techniquestealing techniquecycle stealing techniquecycle bypass technique
7 votes
7 votes
3 answers
3
go_editor asked Jun 23, 2016
4,672 views
Number of chips $(128 \times 8 \;\text{RAM})$ needed to provide a memory capacity of $2048$ bytes$2$$4$$8$$16$
11 votes
11 votes
4 answers
4
go_editor asked Jun 22, 2016
6,556 views
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are$\textsf{INTR & INTA}$$\textsf{RD & WR}$$\textsf{S0 & S1}$$\textsf{HOLD & HLDA}$