0 votes 0 votes Digital Logic made-easy-test-series digital-logic flip-flop + – pranab ray asked Dec 14, 2017 • edited Mar 7, 2019 by Aditi Singh pranab ray 265 views answer comment Share Follow See 1 comment See all 1 1 comment reply raviyogi commented Dec 14, 2017 reply Follow Share i think the ans is mod 3 and the state sequence will be 0,7,3,5,0. there will be no working of nand gate because pr1 is active low and becomes active only when all the inputs to nand gate are 1. that means clock should be 1 for making pr1 active . but the circuit will work only when clk is o because 1st ff is active low. please do share the solution given 0 votes 0 votes Please log in or register to add a comment.