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2 votes
2 votes

A $32$-$bit$ adder is formed by cascading $4$-$bit$ CLA adder.The gate delays (latency)
for getting the sum bits is

  1. $16$
  2. $18$
  3. $17$
  4. $19$
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3 Answers

7 votes
7 votes

A 32 bit adder is formed by  cascading 4 bit CLA adder means 8 4 bit CLA are in one after another in sequence manner.In first,4 bit CLA circuit diagram as you can see that all data are present (A0 A1 A2 A3, B0 B1 B2 B3,C0 also) so for C4 it will take 3 cycles and Sum bits(S0 S1 S2 S3) take 1 more cycles. In this extra 1 cycles C4 will move to next CLA circuit and  make output C5 in 5 cycles and so on.So ,total gate delays=(1st +2nd+3rd+4th+5th+6th+7th+8th)=(3+2+2+2+2+2+2+3)=18 cycles.

If anyone have any doubt please ask me.

0 votes
0 votes

​​​​​​8 four bit CLA are needed to create a 32 bit Adder 

P & G Generator  will take 1 gate delay (as EXOR and AND will operate in parallel) 

Carry generator will take 2 Gate delays (All AND in parallel (1)+All ORs in Parallel(1)=2)

C4 will be available to next CLA and next CLA will Take 2 gate delays also . During same time Sum Generator of first will calculate sums not taking any extra time 

same thing will happen for all 8 carry generators 2*8=16 .During the same time 7 Sum generators will calculate sum without taking extra time as all are working in parallel

Sum generator of last CLA will take 1 gate delay (all EX-or in parallel)

total 1+2*8+1=18

Answer option B

 

–1 votes
–1 votes
18 gate delay
Answer:

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