7.14 A pipeline processor uses the delayed branch technique. You are asked to recommend one of the two possibilities for the design of this processor. In the first possibility, the processor has a four stage pipeline and one delay slot, and in second possibility, it has six stage pipeline with two delay slot. compare the performance of these two alternatives, taking only the branch penalty into account. Assume that 20 percent instruction are branch instruction and that an optimizing compiler has an 80 percent success rate in filling the single delay slot. For the second alternative, the compiler is able to fill the second slot 25 percent of the time.