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Consider a virtual memory system running on a RISC CPU. Page tables are not locked in memory and may be swapped to disk. An 1w (load word) instruction reads one data word from memory; the address is the sum of value in a register and an immediate constant stored in the instruction itself. Neither machine instructions nor page-table entries nor data words can cross a page boundary. In the worst case how many page faults could be generated as a result of the fetch, decode, and execution of an 1w instruction?
asked in Operating System by Active (2.6k points) | 368 views
2 pagefaults, 1 for instruction, 1 for the data word. Assuming 1 level paging
The answer is 4 in question source. I can only think of it as 3 page faults. 1 for instruction, 1 for page fault and 1 for data
yeh i also think 3...1 for  page table 2 for instruction fetching 3rd for operand in load instruction...

now i got is 4 ....

1st for the page table....

2nd for the Instruction Fetching

3rd for the operand effective address calculation...for address we need to go to the coresponding Register address and this also lead a Page fault becoz it also must be in physical memory....

4th for load instruction execution...reading data form memory...

1 word instruction fetch caused a page fault, so the instruction is completely fetched, with the register name/no. ,and the constant to be added specified.

For accessing a register with its name available, we don't need a memory access right?
2 page faults

1 for swap in the disk and

2nd one swap in in page table
actually, it is 4.

for accessing one word, we can get at most 2 page faults. one for the page table when it is swapped and one for the referenced physical address. it is said in the question that we need to consider instruction fetch also. so 2-page faults for instruction fetch and 2 for accessing data word. no page faults for decoding or effective address calculation or from registers as they do not involve paging.

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