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Consider a virtual memory system running on a RISC CPU. Page tables are not locked in memory and may be swapped to disk. An 1w (load word) instruction reads one data word from memory; the address is the sum of value in a register and an immediate constant stored in the instruction itself. Neither machine instructions nor page-table entries nor data words can cross a page boundary. In the worst case how many page faults could be generated as a result of the fetch, decode, and execution of an 1w instruction?

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Answer : 4

Exp :

Fetching lw : CPU has address, say A1, from where to fetch lw.  We’ll look into page table, in worst case, page table may not be present in the memory as it is given in the question that “Page tables are not locked in memory and may be swapped to disk”. So, we bring page table. 1 page fault. Now, it could happen that the page containing lw word is not in memory, so we bring it, 1 page fault. So, fetch cycle, in worst case, may have 2 page faults.

 

Decoding lw : The data word that needs to be loaded has the address A2 which is sum of the value in a register and an immediate constant stored in the instruction lw itself. So, No page fault here.

 

Executing lw :

CPU has address, say A2, of the data word that needs to be loaded.  We’ll look into page table, in worst case, page table may not be present in the memory as it is given in the question that “Page tables are not locked in memory and may be swapped to disk”. So, we bring page table. 1 page fault. Now, it could happen that the page containing the data word is not in memory, so we bring it, 1 page fault. So, execution cycle, in worst case, may have 2 page faults.

Total 4.

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