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A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is:

  1. $\text{11 bits}$
  2. $\text{13 bits}$
  3. $\text{15 bits}$
  4. $\text{20 bits}$
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3 Answers

Best answer
62 votes
62 votes
The page size of $4$ KB. So, offset bits are $12$ bits.

So, the remaining bits of virtual address, $32 - 12 = 20$ bits, will be used for indexing.

Number of sets $= 128/4 = 32 (4$-way set$)  \implies 5$ bits.

So, tag bits $= 20 - 5 = 15$ bits.

Correct option C.
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3 votes
3 votes

The size of virtual address is 32,now page size is 4KB given or,number of bits for offset is 12(2^12=4KB).

                                        Page(20bits)                                              OFFSET(12bits)

Now for TLB header is as:

TAG(y bits) SET(x bits) OFFSET(12bits)

Now the set is given as 4 way set associative,and it can hold 128 entries,

Now to divide 128 entries into 4 sets,number of bits required to do so:

set bits(x)=$128(or,2^7)/(4(or,2^2)))$ 

hence sets bits would be: 5

therefore:

$y+5+12=32$

or,$y=15 bits$

Hence option C is correct

 

1 votes
1 votes
We have a total of 2$^{32}$ memory locations each of 1 B and we are grouping 2$^{12}$ entries each of 1 B. so we will have 2$^{20}$ chunks.Now these chunks are stored in the physical memory and in order to keep track of them we need the page table.to enhance the searching we are using the TLB which has 128 page table entries designed as a 4 way set associative TLB so the number of bits for set offset will be 2$^{5}$ .Earlier we have calculated that no of pages = 2$^{20}$ which is the number of page table entries as well.
So we will divide this 20 into 5 for set offset and rest 15 for the TLB tag bits

Hence option c is correct
Answer:

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