Register

#Instruction-pipeline Data hazard between two consecutive memory access instruction

473 views
0 votes
0 votes
Although the following instructions do not make much sense but if such case occurs, is data forwarding from MA of I1 to MA of I2 allowed? Or will it result in some stall?

Please add some reference, I couldn't find any yet.

I1: Load A     //A<-Mem[address]

I2: Store Adress2, A   // Mem[Address2] <- A
User Avatar

Please log in or register to answer this question.

Voting & Accepting an answer helps improve the community
← PreviousNext →
← Previous in categoryNext in category →

Related questions

2 votes
2 votes
0 answers
1
Shubhanshu asked Sep 28, 2017
1,133 views
Hazard in Pipeline
I know this question is already asked, But here my doubt is different, I have seen many people calculating the RAW hazard without seeing the no of stages in the pipeline which is not correct. In the above question If we see clearly by keeping in the mind that no of ... 2 after the SUB finishes.
I know this question is already asked,But here my doubt is different, I have seen many people calculating the RAW hazard without seeing the no of stages in the pipeline w...
User Avatar
0 votes
0 votes
0 answers
2
Na462 asked Nov 14, 2018
758 views
Data Hazard
User Avatar
0 votes
0 votes
1 answer
3
smsubham asked Dec 27, 2018
461 views
Avoiding pipeline Hazards
Please Confirm.
Please Confirm.
User Avatar
2 votes
2 votes
1 answer
4
Mk Utkarsh asked Oct 23, 2018
2,237 views
Pipeline : Number of RAW dependencies
Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding. I1: ADD R0,R1,R2 (R0=R1+R2) I2: SUB R3,R0,R2 I3:MUL R4,R3,R0 I4:DIV R5,R4,R0 How many RAW dependencies?
Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding.I1: ADD R0,R1,R2 (R0=R1+R2)I2: SUB R3,R0,R2I3:MUL R4,R3,R0I4:D...
User Avatar
Link Copied!