Stall cycle created due to some miss happen in cache and CPU need to access memory
In this question we can see ,
there are $50$ misses in $L_{1}$ cache for which we need to access $L_{2}.$
In $L_{2}$ there are $30$ hits, but again for $200$ misses we need to access Main Memory.
So, total stall cycles are $30*20+20*(20+100)=3000$ stall cycles
Now,
for $500$ memory reference , there are $3000$ stall cycles.
for $1$ memory reference , there are $3000/500$ stall cycles.
Here, each instruction needs $2.5$ memory reference.
So, for $2.5$ memory reference , there are $(3000/500)*2.5=15$ stall cycles or $15 stall/instruction$