Question is not asking about Average memory stall cycles per Instruction
but just Total Stall cycles occur when memory access instruction misses in cache
Total Time on a cache miss => Tīme taken to know that a cache miss occurs + Main Memory (RAM) access time
=> $30 + 80$ ns
=> $110$ ns
Hence, Total stall cycles are extra 80 ns which incurred because of cache miss.
It is given that cycle time = 30 ns
Hence, Total stall cycles are => $\left \lceil \frac{80}{30} \right \rceil$ => $3$
For 2nd question, I guess some important information is missing .