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Directly coming to the question...(its a linked data type qstn)

A pipelined processor with separate instruction and data cache has 5 stages with a cycle time of 30 ns. It is used with copy-back data cache with block size of 1 word. T(cache)=30ns ans T(RAM)=80ns. Hit ratio for cache is 90%. In this cache, if missed word is not passed to the processor until entire block is received from ram.

Q.1. How many stall cycles occur when memory access instruction misses in cache?

A) 1.   B) 2.      C) 3.     D) 4.    

Q.2. What is avg. instruction throughout in MIPS?

 

What I thought was if a normal hit takes 30ns of IF then on miss it should take (block movement + IF from cache) i.e., ({80+30} + 30) ... which will inturn give extra time of 110 ns resulting in 4 stall cycles. But the answer given is different. And based on 1st qstn only you are able to solve second one.

Where am I going wrong??
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Question is not asking about Average memory stall cycles per Instruction

but just Total Stall cycles occur when memory access instruction misses in cache

Total Time on a cache miss => Tīme taken to know that a cache miss occurs + Main Memory (RAM) access time 

                                         => $30 + 80$ ns

                                         => $110$ ns

Hence, Total stall cycles are extra 80 ns which incurred because of cache miss.

It is given that cycle time = 30 ns

Hence, Total stall cycles are => $\left \lceil \frac{80}{30} \right \rceil$ => $3$


For 2nd question, I guess some important information is missing . 

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