914 views
2 votes
2 votes

An instruction pipeline consists of following 5 stages:
                       IF = Instruction Fetch, ID = Instruction Decode, EX = Execute,
                       MA = Memory Access and WB = Register Write Back
Now consider the following code:

Assume that each stage takes 1 clock cycle for all the instructions. The number of clock cycles are required to execute the code, without operand forwarding over a bypass network ________.


Someone please confirm this i am getting 12

1 Answer

0 votes
0 votes

The answer will be 14 cycle without considering split phase(means ID AND WB cant be overlapped)

but as far as GATE is concerned we solve considering split phase (means ID AND WB can be overlapped )

and 12 cycles wil be required

Related questions

0 votes
0 votes
1 answer
4
Sagar475 asked Dec 26, 2021
416 views
Assume that we are using the classic MIPS five-stage(IF, ID, EX, MEM and WB) integer pipeling.