An instruction pipeline consists of following 5 stages:
IF = Instruction Fetch, ID = Instruction Decode, EX = Execute,
MA = Memory Access and WB = Register Write Back
Now consider the following code:
Assume that each stage takes 1 clock cycle for all the instructions. The number of clock cycles are required to execute the code, without operand forwarding over a bypass network ________.
Someone please confirm this i am getting 12