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**For Pipelined system**

There are five stages : S1 S2 S3 S4 S5 with time delays of 2ns, 2ns, 2ns, 3ns, 3ns. Also, the maximum buffer delay is 1ns.

Therefore, T for pipeline = (3+1)ns = 4ns.

Also, Efficiency = 0.8 so, $\frac{1}{S} = 0.8$ or S = $\frac{1}{0.8}$

So, total time taken for 100 instructions = $\left ( 100 + 5 - 1 \right )\frac{1}{0.8}4 = 520$ ns

**For non-pipelined system**

Total time taken = $\left ( 100 \times \left ( 2 + 2+ 2+ 3+ 3 \right ) \right ) = 1200$ ns

**Speedup = $\frac{1200ns}{520ns} = 2.31$**

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**For pipelined processor**

the maximum stage delay is 3ns hence in pipelined processor 1 instruction will take 3ns.

if efficiency of pipeline is 80% means that 80 out of 100 instruction will take 3 ns to complete and 20 instruction will take 5 cycle hence 15 ns to complete therefore

total time taken for 100 instructions in pipeline = 80 x 3 + 20 x 15 => 540ns

**For non-pipelined processor**

Total time taken = 100×(2+2+2+3+3)=>1200 ns

**Speedup = **1200ns / 540ns = 2.22