The L2 and L3 cache memories are divided into a blocks of 5 words.

Question

Suppose there is a system which has 3 levels of cache i.e L1, L2 and L3. The access times of L1, L2 and L3 cache memories are 100 ns/word, 150 ns/word, and 250 ns/word respectively. The L2 and L3 cache memories are divided into a blocks of 5 words. The hit ratio for L1 and L2 are 80% and 90% respectively. What is the average access time?

A. 103ns
B. 108ns
C. 220ns​​​​​​​
D. 112ns

Comments

Yep, @Joshi_nitish​​​​​​​

Same Question - http://db.gateoverflow.in/86072/computer-architecture-11?show=131429

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Hii, @vijay_jr

it is bad to formulate incorrect equation to generate known answer.

0.8*5*100+0.2(0.9*5*150+0.1*250*5)=220

see the highlighted part in your expression, on hit in L1, you will send only referred word(single word) to processor, why are you adding time to send 5 words to processor when it has asked for only one word.

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yes we cannot send all five word at cache hit at L1

Answer 1

Avenge access time =0.8*100+0.2*0.9*150+0.2*0.1*250

                              =220 [simultaneous access if match only that word send to CPU]

Comments

your ans is wrong..it comes as 112 not 220ns