Questions Doubt

Question

Doubt:

1) If its asked that what address does $PC$ hold after execution of $HALT$ what it should be?

2) If the question does not clue about access mechanism for cache what mechanism to hold $hierarchical$ or $simultaneous$?

3) If there is some $additional \  information$ is sent along with $data$ so while calculating efficiency does its transmission considered as useful or not ?

4) If there are $9$ states in a counter and $3$ of them are similar how to find the no of flipflops?

 5)Space complexity should include $stack \  space $ if there is subroutines call along with $auxiliary \  memory$ used?

6)While calculating total no of subnets exclude $2$ or not?

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for ex here in this question i followed standard textbook but its not the case : 

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7)If the word $"minimum"$ is not provided in question then whether i should optimize the $dag$ by removing redundant calculation or not?

8) Processor access $TLB$ first or $Cache$? if its mentioned both then whose access considered first?

Thank you for your time!

Comments

Good collection of Doubts.

1st) for address next to halt instruction will be fetched only when interrupt occur.

ref https://gateoverflow.in/1058/gate2004-63

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2. Hierarchical (as far as I know. Do share if you've come across a question that hints otherwise.)

6. No. Don't subtract 2. That's outdated. I read quite a few answers on this.   

8. Processor accesses TLB first. If it is a miss it goes to the page table. If TLB was a hit it goes to the cache. If it results in a  cache miss, it goes to the main memory.

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I am non getting the point 4..Can u please explain?

Answer 1

nice set of questions..🖐🏻🖐🏻👍🏻

@saxena0612

 

 

1) after HALT instruction the next address is in PC

2) while calculating effective memory access time IF NOTHING IS GIVEN use hierarchical only, But if its said Write Through cache and read write all operations are involved use simultaneous access while WRITING only..

3) no; like if in 1 sec 8 bits are transferred where 3 bits are fir synchronization purpose between sender and receiver then DTR is 5 bps

4) 9 States in counter , 3 are similar;;;;; so 7 states are distinct for which 3 ff's are needed at least, then to distinguish 3 similar states we need 2 ff's at least so IN TOTAL 5 FF'S ARE NEEDED

    EG+++++>>>>

     1,2,0,3,4,0,5,6,0 then repeat..

    for 1,2,3,4,5,6,0 we need 3 ff's ; and for three 0's we need 2 ff's...in total 5

5) Yes ,like in worst case of Quick Sort. Space = 0(n) as stack depth is n which is recursion depth

6) total number of subnets=don't exclude anything.                       total number of useful subnets=exclude 2

7) no "minimum" no optimisation

8) first cache as TLB is generally physically tagged and cache is virtually...so you have to get the physical address first.But physically addressed cache are present also

refer: https://gateoverflow.in/31112/which-is-accessed-frist-tlb-or-cache

 

 

 

 

 

@Arjun@Bikram   **please check Thanks**