Pipelining

Question

Suppose that an unpipelined processor has a cycle time of 25ns, and that it's data path is made up of modules with latencies of 2,3,4,7,3,2 and 4ns(in that order).In pipelining  this processor ,it is not possible to rearrange the order of the modules(for examples, putting the register read stage before the instruction decide stage) or to divide a module into multiple pipeline stages(for complexity reasons). Given pipeline latches with 1ns latency .if the processor is divided into the request number of stages that allow is to achieve the minimum latency from part 1,what is the latency of the pipeline?
(a). no latency
(b). 35 ns latency
(c). 40 ns latency
(d). 56 ns latency

Answer 1

In the question it is “if the processor is divided into the fewest number of stages”

Also, we cannot change the order of the stages, so we can only combine consecutive stages such that maximum stage latency should be 7ns (because it is already highest and we want lowest latency possible). One possible combination could be:

2, (3 + 4), 7, 3, (2 + 4) = 2, 7, 7, 3, 6

k = 5 and max(2, 7, 7, 3, 6) = 7

latch latency = 1ns

therefore,

Latency of the pipeline would be 5*(7+1) = 40ns

Answer 2

latency of pipeline = no of stages * cycle time. now from above no of stages are 7 (2,3,4,7,3,2,4) and cycle time = max(2,3,4,7,3,2,4)+latch latency that is 7+1=8.

 

now latency of pipeline= 7*8=56ns. i think d is the right one.

Comments

I also got the same but answer is 40ns From Madeeasy book.