Count the no. of clocks in a 4 stage pipeline

Question

A 4-stage pipelined processor executed the following loop:

for(i=1;i<=100;i++)

{

I1; I2; I3; I4;

}

What is the no. of clocks to execute the above loop?

a.13    b.15   c.16     d.18

	S1	S2	S3	S4
I1	1	2	1	2
I2	2	1	2	1
I3	1	1	2	1
I4	2	1	2	1

Answer 1

if we use without loop level parallelism than it will take 1100 clock cyles becoz loop is from i=1 to 100
as also for first i=1. it will take 11 cycles similalry for next 100 it will take 1100 cycles...

and with loop level parallelism it will take 11*1+99*7=704 cycle .

Comments

How is it possible that  the1st instruction is taking 11 cycles and the remaining 99 instrs. taking only 7 cycles?( 11*1+99*7=704 ??)

Suppose if there were two iterations then how many cycles would have taken for the 2nd iteration?

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see in fiqure ,i have inserted the I1 instruction in the 7 th clcok cycle.and this I1 instruction time is being shared with the clock time of i4 instruction.. similarly u can see further this time is being shared till 11 clock cycle ..

for the second iteration it will take only 7 clock cycle. becoz 7,8,9,10,11 clcock cycle is being shared in the case of loop level parallelism..see in diagram..and rest 7 clock for remainng.!!

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@Kunal :can u plz xplain wat happens in loop level parallelism.

In order to comprehend this solution I need to have an idea about the concept.