Consider a CPU contains 2000 instructions, there are 80 misses in the L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit time of L1 cache is 5 clock cycles and these are 1.8 memory references per instruction, then average stall per instruction is ________.
Answer given is 9.35.
But I think it should be 6.5.
My Calculations:-
1 inst --------- 1.8 Mem Ref
20000 inst ------- 2000 * 1.8 mem ref = 3600 mem ref.
Miss ratio of L1 = $\frac{80}{3600}$ = 0.05, Hit ratio of L1 = 0.95.
Miss ratio of L2 = $\frac{40}{80}$ = 0.5 = Hit in L2.
Average stalls per instructions = Hit ratio of L1 * Hit in L1 + Miss in L1 * (Hit in L2 + Miss in L2*Miss Penalty of L2).
0.95 * 0 {As there is no stalls when hit in L1 cache} + 0.05(30 + 0.5 * 200)
6.5 stalls/instruction.