Register

IES 2018 JK Flip flop

420 views
1 votes
1 votes
In a master slave JK flip-flop
(a) both master and slave are positive edge triggered
(b) both master and slave are negative edge triggered
(c) master is positive edge triggered and slave is negative edge triggered
(d) master is negative edge triggered and slave is positive edge triggered
User Avatar

1 Answer

Voting & Accepting an answer helps improve the community
← PreviousNext →
← Previous in categoryNext in category →

Related questions

1 votes
1 votes
0 answers
2
sh!va asked Jan 9, 2018
250 views
IES 2018 - Product of sum form
Product of sum form expression leads to what kind of logic circuit? (a) OR-AND circuit (b) NOR-NOR circuit (c) AND-OR-INVERT circuit (d) NAND-NAND circuit
Product of sum form expression leads to what kind of logic circuit?(a) OR-AND circuit(b) NOR-NOR circuit(c) AND-OR-INVERT circuit(d) NAND-NAND circuit
User Avatar
1 votes
1 votes
0 answers
3
sh!va asked Jan 9, 2018
283 views
IES 2018- 8085 programming
In the following 8085 assembly language program, assume that the carry flag is initially reset. What is the content of the accumulator after the execution of the program? MVI A, 04H RRC MOV B, A RLC RLC ADD B RCC (a) 02H (b) 05H (c) 15H (d) 25H
In the following 8085 assembly language program, assume that the carry flag is initially reset. What is the content of the accumulator after the execution of the program?...
User Avatar
2 votes
2 votes
2 answers
4
sh!va asked Jan 9, 2018
2,641 views
IES 2018_Digital Logic_Counter
For what minimum value of propagation delay in each filp-flop will a 10 bit ripple counter skip a count, when it is clocked at 10 MHz? a) 5 ns b) 10 ns c) 20 ns d) 40 ns
For what minimum value of propagation delay in each filp-flop will a 10 bit ripple counter skip a count, when it is clocked at 10 MHz?a) 5 nsb) 10 nsc) 20 nsd) 40 ns
User Avatar
Link Copied!