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Consider the following program which is executed on $4$ stage pipelined processor.

  • IF=$2$ clocks/word
  • ID=$2$ clocks/word
  • EX stage takes $2$ clocks for register operands and $3$ clocks for memory operand
  • WR stage takes $2$ clock cycles for all instructions.
No. Instruction Size in words
     
$I_{1}$ $MOV$  $ \text{R1(R2+300)}$ $3$
$I_{2}$ $ADD$  $R1,R2$ $1$
$I_{3}$ $MOV$  $ \text{(R1+400),R2}$ $3$
$I_{4}$ $MOV$  $ \text{(R2+500),R1}$ $3$

Minimum number of clocks needed to complete the above program is _________________

Note:Pipeline stage sequence is IF,ID,EX and WR

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