search
Log In
3 votes
241 views

in CO and Architecture 241 views
0
4MB/s
0
No ans is given last option
0
post solution here .
0
Sorry to say I didn't have any soln that's why i asked the question that question was given in on of the test series. where ans was last option.
0
4MB/s is correct.

Please log in or register to answer this question.

Related questions

2 votes
0 answers
1
1 vote
0 answers
2
99 views
I got answer 450 but the answer given is 410 400(to access 4 words in L2) + 40(4 access to store word read from L2 in L1) + 10(final one access by CPU) = 450
asked Jan 6, 2018 in CO and Architecture ashish pal 99 views
2 votes
2 answers
3
317 views
Assume we have two dimensional array of size 100x100, each element is occupying 4 bytes and array is stored in row major order. Further assume RAM is 1MB and cache is 4KB with each size of 32 bytes: X: for(i = 0; i < 100; i++){ for(j = 0; j < 100; j++){ { ... } In case of 2-way set associative cache, number of cache misses is(assume initially cache is empty) (A) 1250 (B) 2500 (C) 2400 (D) 2372
asked Dec 24, 2017 in CO and Architecture vishal chugh 317 views
2 votes
2 answers
4
525 views
Common Data For Questions 1 and Question 2 Direct Mapping cache given below 17-tag | 10-block | 5-word , 2 to 1 MUX / OR has latency of 0.6ns ,k-bit comparator has katency of k/10 ns Question 1 If a two- way set associative cache is constructed from the given ... Question 2 Number of MUX/OR and Compators Needed in Direct Mapped Cache (#MUX/OR , Comparator) are (1,17) (17,1) (1024,1) None
asked Dec 4, 2016 in CO and Architecture PEKKA 525 views
...