menu
Login
Register
search
Log In
account_circle
Log In
Email or Username
Password
Remember
Log In
Register
I forgot my password
Register
Username
Email
Password
Register
add
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
Prev
Blogs
New Blog
Exams
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Barc Interview Experience 2020- CSE stream
JEST 2021 registrations are open
TIFR GS-2021 Online Application portal
IIT Jodhpur Mtech AI - Interview Expierence (Summer Admission)
Interview experience at IIT Tirupati for MS program winter admission
Subjects
All categories
General Aptitude
(2.1k)
Engineering Mathematics
(8.5k)
Digital Logic
(3k)
Programming and DS
(5.1k)
Algorithms
(4.5k)
Theory of Computation
(6.3k)
Compiler Design
(2.2k)
Operating System
(4.7k)
Databases
(4.3k)
CO and Architecture
(3.5k)
Computer Networks
(4.3k)
Non GATE
(1.2k)
Others
(1.3k)
Admissions
(595)
Exam Queries
(838)
Tier 1 Placement Questions
(16)
Job Queries
(71)
Projects
(19)
Unknown Category
(1.1k)
Recent Blog Comments
Thanks, dude for sharing your experience !! It...
Congratulations, at least you made it to the...
seems like you really enjoyed the process.......
I wrote an email to IISC regarding JEST 2021 but...
B.Tech students are eligible only for Integrated...
Network Sites
GO Mechanical
GO Electrical
GO Electronics
GO Civil
CSE Doubts
CO: Memory
3
votes
241
views
co-and-architecture
cache-memory
test-series
asked
Jan 11, 2018
in
CO and Architecture
thepeeyoosh
241
views
answer
comment
0
4MB/s
0
No ans is given last option
0
post solution here .
0
Sorry to say I didn't have any soln that's why i asked the question that question was given in on of the test series. where ans was last option.
0
4MB/s is correct.
Please
log in
or
register
to add a comment.
Please
log in
or
register
to answer this question.
0
Answers
← Prev.
Next →
← Prev. Qn. in Sub.
Next Qn. in Sub. →
Related questions
2
votes
0
answers
1
163
views
CO: Cache Memory
asked
Jan 11, 2018
in
CO and Architecture
thepeeyoosh
163
views
co-and-architecture
cache-memory
multilevel-cache
test-series
1
vote
0
answers
2
99
views
Ace Test series: CO & Architecture - Cache Memory
I got answer 450 but the answer given is 410 400(to access 4 words in L2) + 40(4 access to store word read from L2 in L1) + 10(final one access by CPU) = 450
I got answer 450 but the answer given is 410 400(to access 4 words in L2) + 40(4 access to store word read from L2 in L1) + 10(final one access by CPU) = 450
asked
Jan 6, 2018
in
CO and Architecture
ashish pal
99
views
computer-architecture
ace-test-series
test-series
cache-memory
2
votes
2
answers
3
317
views
GateForum Test Series
Assume we have two dimensional array of size 100x100, each element is occupying 4 bytes and array is stored in row major order. Further assume RAM is 1MB and cache is 4KB with each size of 32 bytes: X: for(i = 0; i < 100; i++){ for(j = 0; j < ... of 2-way set associative cache, number of cache misses is(assume initially cache is empty) (A) 1250 (B) 2500 (C) 2400 (D) 2372
Assume we have two dimensional array of size 100x100, each element is occupying 4 bytes and array is stored in row major order. Further assume RAM is 1MB and cache is 4KB with each size of 32 bytes: X: for(i = 0; i < 100; i++){ for(j = 0; j < 100; j++){ { ... } In case of 2-way set associative cache, number of cache misses is(assume initially cache is empty) (A) 1250 (B) 2500 (C) 2400 (D) 2372
asked
Dec 24, 2017
in
CO and Architecture
vishal chugh
317
views
cache-memory
co-and-architecture
test-series
associative-memory
2
votes
2
answers
4
525
views
Calicut Gate Academy Test Series
Common Data For Questions 1 and Question 2 Direct Mapping cache given below 17-tag | 10-block | 5-word , 2 to 1 MUX / OR has latency of 0.6ns ,k-bit comparator has katency of k/10 ns Question 1 If a two- way set associative cache is constructed ... Number of MUX/OR and Compators Needed in Direct Mapped Cache (#MUX/OR , Comparator) are (1,17) (17,1) (1024,1) None
Common Data For Questions 1 and Question 2 Direct Mapping cache given below 17-tag | 10-block | 5-word , 2 to 1 MUX / OR has latency of 0.6ns ,k-bit comparator has katency of k/10 ns Question 1 If a two- way set associative cache is constructed from the given ... Question 2 Number of MUX/OR and Compators Needed in Direct Mapped Cache (#MUX/OR , Comparator) are (1,17) (17,1) (1024,1) None
asked
Dec 4, 2016
in
CO and Architecture
PEKKA
525
views
test-series
co-and-architecture
cache-memory
calicut-gate-academy-test-series
...