virtual address size

Question

Comments

They mean first page table fits in 1 page

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@ Devshree Dubey  thanks a lot :)

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Mention not. :)

Answer 1

Assuming uniform page sizes at all levels.

Then the Logical Address bit representation will be like :-

$\begin{vmatrix} x &x &x & 10 \end{vmatrix}$

10 because Page size = $1 KB$, and $log(1K) = 10$.

Only the outermost page table will be put completely in RAM. Thus,

let Number of bits for indexing into Outermost PT = $x$;

so, Number of entries in this PT = $2^x$

and Given, size of 1 PTE $=4B$.

So, Page Table size $ = 2^x * 4Bytes $

$= 2^x * 2^2 Bytes = 2^{x+2} Bytes$

 

This PT should exactly fit into 1 Page, according to question.

thus  $2^{x+2} = 2^{10}$

$ x + 2 = 10  $

$x = 8$

 

Therefore, our Logical Address bit representation become -> $\begin{vmatrix} 8 &8 &8 & 10 \end{vmatrix}$

Ad required answer is $ 8+8+8+10 = 34  bits$