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5 votes
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A nonpipelined processor operating at 1 MHz is converted into a synchronous pipelined processor with five stages requiring 3.5 μsec, 2.5 μsec, 3 μsec, 2.5 μsec and 3.5 μsec, respectively. The delay of the latches is 1 μsec. The speedup of the pipeline processor for a large number of instructions is ________.
(Upto 2 decimal places)

 

I solve it using speedup= non pipe/pipe

                                     = cpi*t/cpi*

                                     =1*1/1*4.5

                                     =0.22

 

but given ans is 3.33

speedup =(3.5+2.5+3+2.5+3.5)/4.5

              =3.33

why my ans is wrong ? please explain

2 Answers

2 votes
2 votes
Non pipeline means after the completion of first instruction, second instruction will execute, and after the completion of second instruction , third instruction will execute and so on. So we have to sum all the stages delay in case of non pipelined.
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The time needed for non-pipelined process (NP) = Sum of time tor each stages 
               = (3.5 + 2.5 +3+ 2.5 3.5)micro sec
               = 15 micro sec
Time needed for pipelined processor (P)=T,,r- Buffer delay
             Ts = max (all stages rime)
               = max (3.5 + 2.5 +3+ 2.5 + 3.5)1 micro sec
               = 3.5 micro sec
             P =  r- Buffer delay
               = 3.5 pee r- 1 micro sec
               = 4.5 micro sec 
         speedup Non pipeline time / Pipeline time
                 15/4.5 micro sec = 3.3 micro sec ANS
                 

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