CO-Pipelining

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Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 100 instructions I1, I2, I3, …, I100 is executed in this pipelined processor. Instruction I17 is the only branch instruction and its branch target is I91. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is ________ .

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Can you please explain the statement,

( 5 * 1) + ( 16 * 1 ), First 5 is for first instruction, please correct me if iam wrong.
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yes ..for remaining 16 instruction CPI=1 that is what i have written..
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Thanks ..
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thanx dude i want to clear the same logic you have apllied

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5 stage pipeline → 3,6,5,8,4 latencies(in ns).What is average CPI of non pipelined CPU when speed up achieved by to pipeline is 4 ? (ans = 1.23)
A system employs $10$ stage instruction pipeline in which $5$% instruction results in data dependency, $10$% instruction results in control dependency, $2$% instructions results in structural dependency. $10$% instructions are exposed to data and control dependencies. ... dependency and data dependency are $3$ clocks and $2$ clocks respectively. The average instruction time is _______ [in cycles]