Log In
3 votes

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 100 instructions I1, I2, I3, …, I100 is executed in this pipelined processor. Instruction I17 is the only branch instruction and its branch target is I91. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is ________ .

in CO and Architecture 314 views

1 Answer

2 votes

answer will be 612 ns..

Can you please explain the statement,

( 5 * 1) + ( 16 * 1 ), First 5 is for first instruction, please correct me if iam wrong.
yes ..for remaining 16 instruction CPI=1 that is what i have written..
Thanks ..
thanx dude i want to clear the same logic you have apllied

Related questions

2 votes
1 answer
0 votes
1 answer
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)
asked Dec 25, 2018 in CO and Architecture Markzuck 318 views
4 votes
3 answers
Consider a 5 stage pipeline with Instruction Fetch(IF),Instruction decode(ID),Execute(EX),Write back(WB),and Memory access(MA) having latencies(in ns) 3,8,5,6 and 4 respectively. What is average CPI of NON-PIPELINE CPU when speedup achieved by pipelined processor is 4?
asked Dec 18, 2018 in CO and Architecture jatin khachane 1 762 views
1 vote
2 answers
A system employs $10$ stage instruction pipeline in which $5$% instruction results in data dependency, $10$% instruction results in control dependency, $2$% instructions results in structural dependency. $10$% instructions are exposed to data and control dependencies. ... dependency and data dependency are $3$ clocks and $2$ clocks respectively. The average instruction time is _______ [in cycles]
asked Dec 16, 2018 in CO and Architecture zeeshanmohnavi 716 views