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Solving Pipeling Question from https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf

ReIterating the Relevant text here

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You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. Calculate the latency speedup in the following questions.


Note: The solutions given assume the base CPI = 1.4 throughput. Since the question is
ambiguous, you could assume pipelining changes the CPI to 1. The method for computing the
answers still apply

Q4.3) If each pipeline stage added also adds 20ps due to register setup delay, what is the best speedup you can get
compared to the original processor?

-I get how to solve this.

Q4.4) The pipeline from Q4.3 stalls 20% of the time for 1 cycle and 5% of the time for 2 cycles (these occurences are disjoint). What is the new CPI? What is the speedup compared to the original processor?

Given solution

New CPI = 0.2(2.4) + 0.05(3.4) + 0.75(1.4) = 1.7

The solution mentions 0.2*2.4 + 0.05*3.4

how did 2.4 and 3.4 come here?

1 Answer

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