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A $4$-way set-associative cache memory unit with a capacity of $16$ KB is built using a block size of $8$ words. The word length is $32$ bits. The size of the physical address space is $4$ GB. The number of bits for the TAG field is ____

 20 7 5 Tag Set Offset

$<----32---->$

Assume word addressability. (Cache = 4K words; word size = 4B; PAS = 1G words)

 20 7 3 Tag Set Offset

$<----30---->$

Great in both case we obtain the same answer...but in every instance, Will we get the same answer for byte-addressable & word addressable memory?
Yes, same!!
How do you take PAS = 1G words in word addressability?

VAS is 4GB...

Number of sets$=\dfrac{\text{cache size}}{\text{sizeof a set}}$

Size of a set $=\text{blocksize}\times \text{no. of blocks in a set}$
$= 8 \text{ words}\times 4\text{ (4-way set-associative)}$
$= 8\times 4\times 4\text{ (since a word is 32 bits = 4 bytes)}$
$= 128\text{ bytes}.$

So, number of sets $=\dfrac{16\ KB}{(128\ B)}=128$

Now, we can divide the physical address space equally between these $128$ sets.
So, the number of bytes each set can access
$=\dfrac{4\ GB}{128}$

$={32\ MB}$

$=\dfrac{32}{4}=8\text{ M words}=1 \text{ M blocks. ($2^{20}$blocks)}$

So, we need $20$ tag bits to identify these $2^{20}$ blocks.
by

Thanks man
32MB/(size of each block=32 bytes) = 1M blocks

am i right ?
In question, it’s told that the size of the physical address space = 32 GB, what I thought is the size of physical memory is 32GB. Because of which I started to find the number of blocks in physical memory,

Number of blocks =  Physical address space/ block size.

As it’s not mentioned explicitly that cache block size and main memory size are different, so we can assume that both are equivalent. So, what I got is the number of blocks in physical memory is 2^27 which can be accessed using 27 bits. Hence, my total instruction length came out to be 27 bits. I found set bits and word bits correctly, but the remaining was only 15 bits which were finally assigned to the Tag section of instruction.

Please correct me where I am getting wrong.

Irrespective of byte or word addressable system number of bits required for TAG won't get affected

Let us fist assume that system is byte addressable

Block size= 32byte

Number of blocks in main memory= 16KB/32B= 512 blocks

Number of sets = 512/4= 128 sets

Format is TAG |SET | BLOCK

Set= 7 bit,

block = 5 bit,

tag = 32-5-7=20 bits

Now let us consider word addressable system

Convert everything with respect to word

Cache size is 4K words, physical address space is 1G words

Number of blocks in cache= 4K/8=512 blocks

Number of sets = 128 sets

Format = Tag| set | word

Set = 7 bit

Word = 3 bit

Tag =30-7-3= 20 bits

Conclusion irrespective of byte or word addressable system number of bits required for TAG won't be affected provided we define everything as per byte addressable or word addressable system

by

@Srestha,Now I got it. Thanks a lot. :)
Thankssss a lot! Saved me
This should be the best answer with proper editing.

We try to convert in one format either byte addressable or word addressable.both case we will get same tag bits .

### 1 comment

Total number of bits in a physical address should remain be same either u r doing with Byte addressable format(means converting evreything in to bytes) or word addressable please reply if i m wrong somewhere

> Total address length = bits required to represent no of words in Physical Address Space =  Log (Physical address size / Word size)

= Log(4 GB / 32 bits) = 30

> Block size = 8 words = 8 * 32 bits = 32 Bytes

> Bits required for set field = log (cache size / (block size * associativity)) = log(16 KB / (32 Bytes * 4)) = 7

> Bits required for word field = log (no of words in each block) = log 8 = 3

> So bits required for Tag field = 30 - 7 - 3 = 20 bits.