3 votes 3 votes Delay of AND gate = 1ns, FF = 2ns. What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz Digital Logic digital-logic clock-frequency + – Tuhin Dutta asked Jan 18, 2018 • edited Jan 19, 2018 by Tuhin Dutta Tuhin Dutta 950 views answer comment Share Follow See all 18 Comments See all 18 18 Comments reply Show 15 previous comments Tuhin Dutta commented Jan 19, 2018 reply Follow Share As per Made Easy answer is 200MHz. Had been the And Gate applied to the last FF then it would be 5ns for 1 clock cycle to complete 0 votes 0 votes Anu007 commented Jan 19, 2018 reply Follow Share yes ashwin it will be 5nsec. i was confused earlier . :) 1 votes 1 votes srestha commented Jan 19, 2018 reply Follow Share @Ashwin how u calculated? I need to chk it 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes Tclock>=Tpropagation-delay= 2*Tff + Tand-gate=5ns Frequency=1/Tclock=1/5ns=200MHz suvradip das answered Sep 5, 2020 suvradip das comment Share Follow See all 0 reply Please log in or register to add a comment.