The following sequence of instruction is executed in a basic 5 stage pipelined processor (IF, ID, EX, MA and WB). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output present in 4th stage and ALU instruction output is available in 3rd stage. Assume each stage take 1 cycle.
What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding?