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Ace Test Series: CO & Architecture - DMA And Bus Architecture
ashish pal
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Jan 20, 2018
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Answer is D
please explain
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ashish pal
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Jan 20, 2018
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Akshay Koli 4
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i'm getting 4MBps
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If cycle time it reduced to half and number of cycles are same , so to transfer same amount of data we will need double bandwidth as we required earlier ie 4MBPS
Mohnish
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A hard disk with a transfer rate of 1 KBps is constantly transferring data to memory using DMA cycle stealing mode. The size of the data transfer is 16 bytes. The processor runs at 400 kHz clock frequency. The DMA controller requires ... time as 0.9375 sec and percentage time CPU gets blocked = transfer time/preparation time (IN case of cycle stealing)
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MadeEasy Subject Test: CO & Architecture - Dma
Consider $1 \text{ MBPS}$ hard disk is interfaced to the processor in a cycle stealing mode of $\text{DMA}$ whenever $64$ bytes of the data is available in the buffer then it is transferred to the main memory. Processor word length is $64$ bits ... $\text{CPU}$ time is consumed for the $\text{DMA}$ operation is ________ (in $\%$).
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sidsunny
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MadeEasy Subject Test: CO & Architecture - Dma
I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. before and after that it can do its own work. Where am I wrong?
sidsunny
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