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Consider the following Instruction sequence
I2: LW R2,0(R1)
I3: LW R1,4(R1)
I4: OR R3,R1,R2
And assume following five stage pipeline with following stages:
IF,ID,EXE,MEM,WB
The no of RAW hazards in the above Instruction sequence is?
(A) 3
(B) 2
(C) 4
(D) 1

Note:- I think there are 2 RAW hazards, b/w I1 & I2 and I3&I4.

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Is ans 4??
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btw, can you explain?
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I got I1-I2 , I1-I3 ,I2-I4 ,I3-I4

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yes i'm also getting 4 RAW hazards.but i think in instruction second after loading a word from memory location we can eliminate dependency at third instruction isn't it?
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@srestha, RAW dependecies are 4 but RAW hazard are 3 only,

b/w I1-I2, I1-I3 and I3-I4
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@joshi_nitish
I havenot got u?
I4 of R2  is still dependent on I2
So, why not I2-I4??
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yes, sorry.

i hadn't seen I2-I4, there will be 4 RAW hazard.
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@nitish don't you think, when instruction I3 needs R1, I1 would update it, why is RAW hazard then?

because I2 will stall pipeline until I1 updates R1, and when I3 executes it will get updated value of R1.
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Can someone answer why is there a hazard between I1 and I3, because until I2 completes I3 can't complete.
and I2 completes after I1 updates R1, right?
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I  understand ur point

A very good point u cited

But where is stall in I2 ?? and why there should be stall?? each instruction need 1 cycle only right?

Can u draw it plz

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@joshi_nitish

I think

if there is stall, there shouldnot be any WAW hazard

But is there be any stall??

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Correct me If I am wrong :

Considering absence of Operand Forwarding (because, it is not given in the question), I think there are 3 RAW hazards between I1-I2, I2-I4 and I3-I4.

RAW Hazards----> Read After Write hazard is created when the instruction "j" tries to read the data before the instruction "i" writes it. It is also called True data dependency. It checks only for adjacent instructions.

In the above question,

there are 2 RAW hazards between I1,I2 and I3,I4.

option b.

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I2-I4 also for R2
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while counting RAW hazards, we will consider only adjacent instructions.

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