Consider the following Instruction sequence
I1: ADD R1,R2,R1
I2: LW R2,0(R1)
I3: LW R1,4(R1)
I4: OR R3,R1,R2
And assume following five stage pipeline with following stages:
The no of RAW hazards in the above Instruction sequence is?
Note:- I think there are 2 RAW hazards, b/w I1 & I2 and I3&I4.
I got I1-I2 , I1-I3 ,I2-I4 ,I3-I4
@ Vijay Thakur
I understand ur point
A very good point u cited
But where is stall in I2 ?? and why there should be stall?? each instruction need 1 cycle only right?
Can u draw it plz
if there is stall, there shouldnot be any WAW hazard
But is there be any stall??
RAW Hazards----> Read After Write hazard is created when the instruction "j" tries to read the data before the instruction "i" writes it. It is also called True data dependency. It checks only for adjacent instructions.
In the above question,
there are 2 RAW hazards between I1,I2 and I3,I4.