Gateforum Test Series

Question

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My solution:

Avg time = 0.84*1 + 0.16*0.92*(5+1) + 0.16*.08*(1+5+50) = 2.44 cycles...but apparently he correct answer is 5.8

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1+0.16(5+0.5(50))=5.8 cycles

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Can you please elaborate. Thanks!

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See,

first 100 access to L1=100*1=100 cycles

16 misses go to L2=16*2(L2 access time)=16*5=80

8 misses from L2=8*50=400

100+80+400=580,This is for 100 mem references,580/100=5.8

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Okay..got it!! Thanks!

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What is wrong with @Sumaiya23 solution can you please tell.

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@vishal

   100 memory references.

           |

           |

          \|/

 _____________

| L1 Cache       | //84 hits in L1 cache itself.

|_____________|

 Remaining 16 references

           |

           |

          \|/

 ____________

| L2 Cache     | //Given, Out of 16 references made to L2,  8 hits in L2 cache i.e. 8 misses.

|____________| //Therefore, hit ratio = miss ratio = 0.5  for L2 cache.

 Remaining 8 references

           |

           |

          \|/

 ________________

| Main Memory    |

|_______________ |

Therefore, Avg time = 0.84*1 + 0.16*0.5*(5+1) + 0.16*0.5*(1+5+50)

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Thanks again for this answer :)

Answer 1

correct answer will be = 5.8

Average memory access time=1+(16/100)*(5+(8/16)*50)=5.8

Average memory access time=hit time of L1+miss rate of L1*(hit time of L2+miss rate of L2*miss penalty of L2 to memory)