A 4-bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 100 ns,
the maximum clock frequency that can be used is equal to:
Ans 2.5MHz.
I think it should be $\frac{1}{16*10^{-7}} = 0.625MHz$
Consider a system employing interrupt driven input/output for a particular device that transfers data at an average of 16KB/s on a continuous basis. Assume that interrupt processing takes 50 μsec (i.e., the jump to the Interrupt Service Routine (ISR),execute it and return to main program). The fraction of processor time is consumed by this input/output
device if it interrupt for every byte is ______ (upto 3 decimal places).
Suppose A, B, C, D, E, F are sorted sequence having length 20, 30, 70, 55, 120, 60. They are to be merged into a single sequence by merging together two sequence at a time. The minimum number of comparisons that will be needed in the worst case by the optimal algorithm for doing this is
Ans = 840
I am getting 860.
