1 votes 1 votes CO and Architecture ace-test-series co-and-architecture cache-memory + – Manis asked Jan 28, 2018 • edited Mar 3, 2019 by I_am_winner Manis 379 views answer comment Share Follow See all 5 Comments See all 5 5 Comments reply hs_yadav commented Jan 28, 2018 reply Follow Share manis ur answer is correct it is 22 bits.... for 4-set ass..it is 20 and for 16-set asso...it is 22bits 0 votes 0 votes Manis commented Jan 28, 2018 reply Follow Share yea. i think i am right. but the solution provided by them was bit confsing so i prefer to discuss here.... 0 votes 0 votes hs_yadav commented Jan 28, 2018 reply Follow Share could u please post the given answer....i also see this question one more time with same answer...i want to varify it... 0 votes 0 votes Manis commented Jan 28, 2018 reply Follow Share this was given explaination.... 0 votes 0 votes hs_yadav commented Jan 28, 2018 reply Follow Share oh!!! now i got it .... here solution is according to assumption that memory is word addressable...and our solution s based.on byte addressing system... i think they must specify separately about it....?but in gate exam every thing would be cleared... 0 votes 0 votes Please log in or register to add a comment.
