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+34 votes

In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

  1. A smaller block size implies better spatial locality
  2. A smaller block size implies a smaller cache tag and hence lower cache tag overhead
  3. A smaller block size implies a larger cache tag and hence lower cache hit time
  4. A smaller block size incurs a lower cache miss penalty
asked in CO & Architecture by Veteran (113k points)
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4 Answers

+64 votes
Best answer
  1. A smaller block size means during a memory access only a smaller part of near by addresses are brought to cache- meaning spatial locality is reduced.
  2. A smaller block size means more number of blocks (assuming cache size constant) and hence index bits go up and offset bits go down. But the tag bits remain the same.
  3. A smaller block size implying larger cache tag is true, but this can't lower cache hit time in any way.
  4. A smaller block size incurs a lower cache miss penalty. This is because during a cache miss, an entire cache block is fetched from next lower level of memory. So, a smaller block size means only a smaller amount of data needs to be fetched and hence reduces the miss penalty (Cache block size can go til the size of data bus to the next level of memory, and beyond this only increasing the cache block size increases the cache miss penalty).
answered by Veteran (379k points)
edited by
Reducing block size also means we need to move more blocks in cache than earlier for same amount of data, means more number of accesses in case of cache miss. Doesnt this translates to increased cache miss penalty? Why reduced block size **always** reduces cache miss penalty?
great explanation @Arjun sir
@srestha,Please may I know one thing Srestha.If there is a larger block size of Cache,will it not accommodate larger data as compared to a cache with a smaller block size?Here, the no of tags required will be less.But in case of cache with smaller block size and more no of tags there will be more overhead?Please correct me if wrong.
Although, exploiting a spatial locality doesn't always lead to a lower miss rate, As we have seen if we access 2d array column wise and it is originally stored in memory in row order.
Can anyone explain the third point that @sachin Mittal said about temporal locality

How temporal locality will lead to increase in miss rate.?
hence index bits go up and offset bits go down. But the tag bits remain the same. ?how tag bit remain same?

@Prince Sindhiya   Third point of @sachin sir is

Initially say our block size is very small then we can accommodate more no. of blocks in cache this implies we can store more number of distinct accesses hence high temporal locality ( because if they will be accessed in near future then there are more chances of them being a hit). But this case has very low spatial locality as we have brought in lesser number of words due to small block size this implies if words near our previous accesses are referenced then there is a high chance of it being a miss. As we consider an average process execution scenario where both temporal and spatial accesses are equally likely, so in this case number of spatial access misses will be way higher due to which net miss rate will be higher.

Now, if say we gradually increase the block size then we are reducing the number of blocks in the cache which means little lower temporal locality but on the other hand, we are getting higher spatial locality so net miss rate will reduce. So, we can see that a trade-off is going on between temporal and spatial locality. Now, increasing block size further will at some point land us on min. point of the miss rate curve (this is actually the trade-off point).

But if we further increase block size then temporal locality is very small while spatial is more, so again miss rate starts to rise.

Reducing the block size could lead to increase in miss rate because of spatial locality as less number of bytes will be transferred to the block. So decreasing block size decreases miss penalty and increases miss rate .

@Arjun-Sir can we say that smaller block size, will increase tag bits, hence width of tag comparator will increase.So, the cache hit time will surely increase and never decrease for option (C).


@Ayush Upadhyaya "Surely increase" may not be true as tag comparison happens in parallel. 

+9 votes
Block : The memory is divided into equal size segments. Each segment is called a block. Data in cache is retrieved in form of blocks. The idea is to use Spatial Locality (Once a location is retrieved, it is highly probable that the nearby locations would be retrieved in near future).

TAG bits : Each cache block is given a set of TAG bits to identify which main memory block is present in that cache block.

Option A : If the block size is small, there would be less number of near-by address for future references by CPU to be present into that block. Hence this is not better spatial locality.

Option B : If the block size is smaller, no of blocks would be more in cache, hence more cache tag bits would be needed, not less.

Option C : Cache tag bits are more ( because more no of blocks due to smaller block size ), but more cache tag bits can't lower the hit time ( even it will increase ).

Option D : If there is a miss at cache memory ( i.e. the needed block by the CPU is not present in the cache memory ), then that block has to be moved from next lower level of memory ( lets say main memory ) in the memory hierarchy, and if the block size is lower, then it takes less time to be placed into cache memory, hence less miss penalty. Hence option D.
answered by Loyal (9.2k points)
edited by

@  Regina Phalange

what is miss penalty..??

no. of times miss occur or time taken to placed a block from lower level to cache memory...??

as u said " if the block size is lower, then it takes less time to be placed into cache memory, hence less miss penalty

plzzz explain more... i m little bit confused now :( 

+6 votes
D option makes perfect sense as there is no relation between tagbits and size of block/lines in caching
answered by (71 points)
+1 vote

A) This is wrong. Spatial locality reduces on reducing block size.

B) Tag bit do not change on changing block size, only cache tag overhead will increase on small block size.

(Suppose we have address space of 20bits, 16KB cache size , 16Byte block size then offset bit 4, line bit 10(Directed mapped), tag bit 6. Now keep everything same and change block size to 64Byte then offset bit 4, line bit 8 but tag bit will be same 10.)

C) same explanation as option B. But no effect on cache hit time because searching in cache is parallel execution (in all mapping technique.) all comparators and multiplexers work in parallel. 

D) The answer is D. Suppose there is a data bus between L1 & L2 cache of size 8 word and L1 cache size=4word L2 cache size=16word. If a miss occurred in L1 cache only 4 word has to be transferred from L2 cache to L1 cache and this will take half second to transfer but if we increase size of L1 cache to 8Word then it will take more time. 

answered by Active (1.5k points)
option d explanation not understand

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