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In designing a computer's cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

  1. A smaller block size implies better spatial locality
  2. A smaller block size implies a smaller cache tag and hence lower cache tag overhead
  3. A smaller block size implies a larger cache tag and hence lower cache hit time
  4. A smaller block size incurs a lower cache miss penalty
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  1. A smaller block size means during a memory access only a smaller part of near by addresses are brought to cache- meaning spatial locality is reduced.
     
  2. A smaller block size means more number of blocks (assuming cache size constant) and hence index bits go up and offset bits go down. But the tag bits remain the same.
     
  3. A smaller block size implying larger cache tag is true, but this can't lower cache hit time in any way.
     
  4. A smaller block size incurs a lower cache miss penalty. This is because during a cache miss, an entire cache block is fetched from next lower level of memory. So, a smaller block size means only a smaller amount of data needs to be fetched and hence reduces the miss penalty (Cache block size can go till the size of data bus to the next level of memory, and beyond this only increasing the cache block size increases the cache miss penalty).

Correct Answer: $D$

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Block : The memory is divided into equal size segments. Each segment is called a block. Data in cache is retrieved in form of blocks. The idea is to use Spatial Locality (Once a location is retrieved, it is highly probable that the nearby locations would be retrieved in near future).

TAG bits : Each cache block is given a set of TAG bits to identify which main memory block is present in that cache block.

Option A : If the block size is small, there would be less number of near-by address for future references by CPU to be present into that block. Hence this is not better spatial locality.

Option B : If the block size is smaller, no of blocks would be more in cache, hence more cache tag bits would be needed, not less.

Option C : Cache tag bits are more ( because more no of blocks due to smaller block size ), but more cache tag bits can't lower the hit time ( even it will increase ).

Option D : If there is a miss at cache memory ( i.e. the needed block by the CPU is not present in the cache memory ), then that block has to be moved from next lower level of memory ( lets say main memory ) in the memory hierarchy, and if the block size is lower, then it takes less time to be placed into cache memory, hence less miss penalty. Hence option D.
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A) This is wrong. Spatial locality reduces on reducing block size.

B) Tag bit do not change on changing block size, only cache tag overhead will increase on small block size.

(Suppose we have address space of 20bits, 16KB cache size , 16Byte block size then offset bit 4, line bit 10(Directed mapped), tag bit 6. Now keep everything same and change block size to 64Byte then offset bit 4, line bit 8 but tag bit will be same 10.)

C) same explanation as option B. But no effect on cache hit time because searching in cache is parallel execution (in all mapping technique.) all comparators and multiplexers work in parallel. 

D) The answer is D. Suppose there is a data bus between L1 & L2 cache of size 8 word and L1 cache size=4word L2 cache size=16word. If a miss occurred in L1 cache only 4 word has to be transferred from L2 cache to L1 cache and this will take half second to transfer but if we increase size of L1 cache to 8Word then it will take more time. 

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