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If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?

  1. Width of tag comparator
  2. Width of set index decoder
  3. Width of way selection multiplexer
  4. Width of processor to main memory data bus
asked in CO & Architecture by Veteran (112k points)
retagged by | 2.3k views
+1
I think width of any type of BUS is not affected by associativity of cache whether it is processor to main memory bus OR  bus internal to the CPU!!

1 Answer

+35 votes
Best answer

If associativity is doubled, keeping the capacity and block size constant, then the number of sets gets halved. So, width of set index decoder can surely decrease - (B) is false.
Width of way-selection multiplexer must be increased as we have to double the ways to choose from- (C) is false

As the number of sets gets decreased, the number of possible cache block entries that a set maps to gets increased. So, we need more tag bits to identify the correct entry. So, (A) is also false.

(D) is the correct answer- main memory data bus has nothing to do with cache associativity- this can be answered without even looking at other options.

answered by Veteran (370k points)
edited by
+15

D) Width of processor to Main Memory Data Bus


+1
sir i did not understand the way selection part, if there are 2 blocks in a set and the tag is k bits then there will be 2* k multiplexers,if there are 4 blocks in a set and the tag is k bits then 4 * k multiplexers, but what role or which one is the way selection multiplexer?
+8
"way" is for no. of blocks in a set. For $k-way$, all $k$ blocks in a set are compared simultaneously using tag comparator and the matching one is multiplexed using a $k-way$ multiplexer.
+1
got it sir :)
+2
@arjun sir...What is the difference between way selection multiplexer and set index decoder.

Please explain...
+1
decoder is used to find, which set to look into? it takes set field bits of address as input.

while a multiplexer takes tag bits of cache lines as input and output of these multiplexers is given to comparator that compares them with tag of the address.
+1
can you explain with a diagram..
0
Hi Sir , getting confussed with the way selction multiplexer . Sir when it is asking for way seleection multiplexer then does it means no of mux required to compare tag bits
+6

width of way selection multiplexer means finding the size of multiplexer as per how many input lines are there .

+10

......................

0
Where is decoder??????
+2
See the 8 set bits in the figure and for any particular combination of those 8 bits, a set out of 256 possible ones is selected. This is done by the decoder -- not explicitly shown in the above figure.
0
How to visualise this figure
0
Arjun Sir good explanation
0
Main memory data bus has nothing to do with cache even if we double the associativity by maintaining the block size and capacity unchanged.
0
what are the select lines to mux? for 4x1 there should be 2 select lines? I can see four..please explain
0

@Debashish Deka here mux is just selecting datas and what are these 4 tables denote?

All have same index,ple ple clarify.

0

@vineet.ildm here first we have to select a set with the help of the decoder and then after selecting that set ,we have to select a block from that set by comparing all tag bits of the blocks of that particular set with the help of the multiplexer.

Am I wrong?

0
no of multiplexers is equal to no of data bits ??
Answer:

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