If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
If associativity is doubled, keeping the capacity and block size constant, then the number of sets gets halved. So, width of set index decoder can surely decrease - (B) is false.
Width of way-selection multiplexer must be increased as we have to double the ways to choose from- (C) is false
As the number of sets gets decreased, the number of possible cache block entries that a set maps to gets increased. So, we need more tag bits to identify the correct entry. So, (A) is also false.
(D) is the correct answer- main memory data bus has nothing to do with cache associativity- this can be answered without even looking at other options.
D) Width of processor to Main Memory Data Bus
width of way selection multiplexer means finding the size of multiplexer as per how many input lines are there .
@Debashish Deka here mux is just selecting datas and what are these 4 tables denote?
All have same index,ple ple clarify.
@vineet.ildm here first we have to select a set with the help of the decoder and then after selecting that set ,we have to select a block from that set by comparing all tag bits of the blocks of that particular set with the help of the multiplexer.
Am I wrong?
I think the translation looks like Tag=29...
What significance does this line holds in this...