MadeEasy Test Series: CO & Architecture - Addressing Modes

Question

A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directory entry contains, in addition to tag address, 1 valid bit and 1 matching bit. The size of cache tag directory is ________ (in KB).

---

Given solution: 

---

My answer:

Exactly as above till here:

TAG Size = $23\ bits * 2^{14}$

                = $3\ bytes * 2^{14}$

                = 48 KB

Comments

why tag bits must be a multiple of a byte?

---

Sir, there will be 2^14 entries and each entry will contain the tag with 2 other bits. We generally have memory chips arranged in bytes, like 1024 X 8. We don't have memory like 1024 X 23 . No?

---

Or else it can be done this way :
$\frac{23}{2^3}\times2^{14}=23\times2^{14-3}=23\times 2\text{ KB}=46\text{ KB}$

---

We do have that at this level. Will get you some figures if I can find.

---

Ok Sir. Thanks. So do we also use such memory in microprogrammed control unit? In case we get one microword of size, say 13 bits.

---

answer will be 46 KB