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suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of the L1 cache is 1 clock cycle. what is average memory access time?
in CO and Architecture by Loyal (5.7k points) | 72 views
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is it correct way .96*1 + .04*(.98*11+.02*(111))

1.48

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hit ratio of l2 is calculated wrong
by Active (2.7k points)
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okkk got it i have to take local miss rate instead of global miss rate thanks
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Answer 3.4 clock cycle

This based on global miss rate and local miss rate

by Loyal (5.7k points)

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