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Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 100 instructions I1, I2, I3, …, I100 is executed in this pipelined processor. Instruction I17 is the only branch instruction and its branch target is I91. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is ________ .
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34 cycles is required total, but what is the time reqd for each instruction in ns?
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@Arjun sir
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34 * 18 = 612 ns

+1 vote
untill 17 instruction there is no problem in pipelining because no instruction is branch instruction .$17^{th}$ is branch instruction and target address is available at execution stage($4^{th}$) of pipelining ,due to which next three instructions inserted in pipeline wrongly.after that target address will be available and control will be transferred  to instruction 91 after that all instruction will be execute .

so total no. of instructions which are available in pipeline =17+3+10=30.

total time to complete these instructions ={5+(30-1)}*18 ns

=34*18 ns=612 ns.

+1 vote