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Consider a pipelined processor having 5 stages. The stage delays are 1, 1.4, 1.2, 3, 2ns and interstage buffer delays are 1ns. The 3rd stage is capable of deciding branch target address. The processor starts fetching new instruction when the conditional branch outcome is known. 30% of instructions are the conditional branch, then calculate the execution time for 1200 instructions?
in CO and Architecture by Active (1.4k points) | 72 views

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this is solution ...JUST ONE CORRECTION...

1920 are CLOCKS NEEDED...its not answer ..

so answer will be 1920*4 nano sec=7680 nano sec

by Boss (11k points)

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