2 votes 2 votes The time delays of 4 segments are 60 ns, 70 ns, 100 ns and 80 ns respectively. Interface registers are have the delay of 10 ns. what is the speed up? a. 2.9 b. 2.6 c. 3.2 d. 1.8 CO and Architecture co-and-architecture pipelining speedup + – khushtak asked Oct 19, 2015 • retagged Nov 13, 2017 by Arjun khushtak 5.3k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
Best answer 2 votes 2 votes S= tn/ tp = S1 + S2 +S3 + S4 / max (S1+10 , S2+10, S3+10, S4+10) =60+70+100+80/max(60+10, 70+10, 100+10,80+10) = 310/110=2.818 ≃2.9 option A Umang Raman answered Oct 19, 2015 • selected Dec 15, 2015 by Pooja Palod Umang Raman comment Share Follow See 1 comment See all 1 1 comment reply shipra tressa commented Dec 2, 2018 reply Follow Share one doubt, in pipeline is their any need of adding the buffer in the last stage?? 0 votes 0 votes Please log in or register to add a comment.
1 votes 1 votes Tn = Time to execute N instructions in a non-pipelined design =60 + 70 +100 + 80 + 10 = 320 Tp= Time to execute N instructions in a pipelined design =100 +10 =110 Speed Up = Tn / Tp = 320 / 110 =2.9 LeenSharma answered Oct 19, 2015 LeenSharma comment Share Follow See all 3 Comments See all 3 3 Comments reply Umang Raman commented Oct 19, 2015 reply Follow Share Do we need interface register in non-pipe? what is the use of Interface register in Non-pipeline? 0 votes 0 votes LeenSharma commented Oct 19, 2015 reply Follow Share if in the question they have mention the buffer delay or interstage delay then we have to consider it . Interface register is used for interstage transfer of data (Buffer overhead) and it is same for all the stages. 1 votes 1 votes Umang Raman commented Oct 19, 2015 reply Follow Share inter stage transfer is done none pipeline to if yes then why you are adding only one inter register delay there are 4 stages? 0 votes 0 votes Please log in or register to add a comment.
1 votes 1 votes Speed Up = Time Without Pipeline / Time With Pipeline = (60 +70 + 100 + 80) / max(60,70,100,80) + 10 = 310/ 110 = 2.8 You might get a doubt why we did not included interstage buffer delay in Non Pipeline. It is because it is used in pipeline for operand forwarding from one stage to other. But in Non Pipeline since we are executing one instruction at a time. So there is no operand forwarding and therefore not required. Mehak Sharma 1 answered Dec 12, 2016 Mehak Sharma 1 comment Share Follow See all 0 reply Please log in or register to add a comment.