gate 2018 cs

Question

physical address space of the omputer system is 2^p bytes , word size is 2^w bytes , cache memory has 2^n bytes and cache block size is 2^m words,k-way set associative is used for mapping from main memory to cache memory .the size of the tag bit is???

Comments

They have not mentioned anything so let it byte addressable

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@Ashwin Kulkarni bro when they gave 2^w Bytes as one word the physical address size will be 2^(P-W) and the memory is word addressable every word gets a address 

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P-w-n-logk bits

Answer 1

As per given data:
PAS = 2^p  B

WS = 2^w B

CS = 2ⁿ B

BS = 2^m _{Words ⁼} 2^{m *} 2^w B _⁼ 2^(m+w) B

K - way set associative

Tag Bit

Set No

Block Offset

# of lines = CS/BS = 2^(n-m-w) 

# of sets = #of lines / K = 2^(n-m-w)/K

Set_no: log [ 2^(n-m-w)/K ] = n - m - w - log K

Tag Bit = p - set_no - block offset = p - n + log K

Comments

good answer

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Block offset = m bits

So, the answer comes out to be ( p-n+w+log k )

Answer 2

I think it will be

P - w-n-logk bits, assuming word addressable memory. Don't forget to add the offset bits also.

No. Of bits in offset is m,

No. Of bits in sets in w-m-n-logk

So, no of tag bits are p - set_bits + offset_bits.

Answer 3

Physical memory is of size 2^P bytes.
Each word is of size 2^W bytes.
Number of words in physical memory = 2^(P-W)
So the physical address is P-W bits
Cache size is 2^N bytes.
Number of words in the cache = 2^(N-W)
Block size is 2^M words
No. of blocks in the cache = 2^(N-W-M)
Since it is k-way set associative cache, each set in the cache will have k blocks.
No. of sets = 2^(N-W-M ) / k
SET bits = N-W-M-logk
Block offset = M
TAG bits = P-W-(N-M-W-logk)-M = P-W-N+M+W+logk-M = P - N + logk